? 2005 fairchild semiconductor corporation ds009915 www.fairchildsemi.com november 1988 revised february 2005 74ac10 ? 74ACT10 triple 3-input nand gate 74ac10 74ACT10 triple 3-input nand gate general description the ac/act10 contains three, 3-input nand gates. features i cc reduced by 50% on 74ac only outputs source/sink 24 ma ordering code: device also available in tape and reel. specify by appending suffix letter ?x? to the ordering code. pb-free package per jedec j-std-020b. note 1: ?_nl? indicates pb-free package (per jedec j-std-020b). use this number to order device. logic symbol ieee/iec connection diagram pin descriptions order number package number package description 74ac10sc m14a 14-lead small outline integrated circuit (soic), jedec ms-012, 0.150" narrow 74ac10sj m14d pb-free 14-lead small outline package (sop), eiaj type ii, 5.3mm wide 74ac10mtc mtc14 14-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide 74ac10pc n14a 14-lead plastic dual-in-line package (pdip), jedec ms-001, 0.300" wide 74ac10pc_nl (note 1) n14a pb-free 14-lead plastic dual-in-line package (pdip), jedec ms-001, 0.300" wide 74ACT10sc m14a 14-lead small outline integrated circuit (soic), jedec ms-012, 0.150" narrow 74ACT10pc n14a 14-lead plastic dual-in-line package (pdip), jedec ms-001, 0.300" wide pin names description a n , b n , c n inputs o n outputs
www.fairchildsemi.com 2 74ac10 74ACT10 absolute maximum ratings (note 2) recommended operating conditions note 2: absolute maximum ratings are those values beyond which damage to the device may occur. the databook specifications should be met, with- out exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. fairchild does not recommend operation of circuits outside databook specifications. dc electrical characteristics for ac note 3: all outputs loaded; thresholds on input associated with output under test. note 4: maximum test duration 2.0 ms, one output loaded at a time. note 5: i in and i cc @ 3.0v are guaranteed to be less than or equal to the respective limit @ 5.5v v cc . supply voltage (v cc ) 0.5v to 7.0v dc input diode current (i ik ) v i 0.5v 20 ma v i v cc 0.5v 20 ma dc input voltage (v i ) 0.5v to v cc 0.5v dc output diode current (i ok ) v o 0.5v 20 ma v o v cc 0.5v 20 ma dc output voltage (v o ) 0.5v to v cc 0.5v dc output source or sink current (i o ) r 50 ma dc v cc or ground current per output pin (i cc or i gnd ) r 50 ma storage temperature (t stg ) 65 q c to 150 q c junction temperature (t j ) pdip 140 q c supply voltage (v cc ) ac 2.0v to 6.0v act 4.5v to 5.5v input voltage (v i ) 0v to v cc output voltage (v o ) 0v to v cc operating temperature (t a ) 40 q c to 85 q c minimum input edge rate ( ' v/ ' t) ac devices v in from 30% to 70% of v cc v cc @ 3.3v, 4.5v, 5.5v 125 mv/ns minimum input edge rate ( ' v/ ' t) act devices v in from 0.8v to 2.0v v cc @ 4.5v, 5.5v 125 mv/ns symbol parameter v cc t a 25 q ct a 40 q c to 85 q c units conditions (v) typ guaranteed limits v ih minimum high level 3.0 1.5 2.1 2.1 v out 0.1v input voltage 4.5 2.25 3.15 3.15 v or v cc 0.1v 5.5 2.75 3.85 3.85 v il maximum low level 3.0 1.5 0.9 0.9 v out 0.1v input voltage 4.5 2.25 1.35 1.35 v or v cc 0.1v 5.5 2.75 1.65 1.65 v oh minimum high level 3.0 2.99 2.9 2.9 output voltage 4.5 4.49 4.4 4.4 v i out 50 p a 5.55.495.4 5.4 v in v il or v ih 3.0 2.56 2.46 i oh 12 ma 4.5 3.86 3.76 v i oh 24 ma 5.5 4.86 4.76 i oh 24 ma (note 3) v ol maximum low level 3.0 0.002 0.1 0.1 output voltage 4.5 0.001 0.1 0.1 v i out 50 p a 5.5 0.001 0.1 0.1 v in v il or v ih 3.0 0.36 0.44 i ol 12 ma 4.5 0.36 0.44 v i ol 24 ma 5.5 0.36 0.44 i ol 24 ma (note 3) i in maximum input 5.5 r 0.1 r 1.0 p av i v cc (note 5) leakage current or gnd i old minimum dynamic 5.5 75 ma v old 1.65v max i ohd output current (note 4) 5.5 75 ma v ohd 3.85v min i cc maximum quiescent 5.5 2.0 20.0 p av in v cc (note 5) supply current or gnd
3 www.fairchildsemi.com 74ac10 74ACT10 dc electrical characteristics for act note 6: all outputs loaded; thresholds on input associated with output under test. note 7: maximum test duration 2.0 ms, one output loaded at a time. ac electrical characteristics for ac note 8: voltage range 3.3 is 3.3v r 0.3v voltage range 5.0 is 5.0v r 0.5v ac electrical characteristics for act note 9: voltage range 5.0 is 5.0v r 0.5v capacitance symbol parameter v cc t a 25 q ct a 40 q c to 85 q c units conditions (v) typ guaranteed limits v ih minimum high level 4.5 1.5 2.0 2.0 v v out 0.1v input voltage 5.5 1.5 2.0 2.0 or v cc 0.1v v il maximum low level 4.5 1.5 0.8 0.8 v v out 0.1v input voltage 5.5 1.5 0.8 0.8 or v cc 0.1v v oh minimum high level 4.5 4.49 4.4 4.4 vi out 50 p a output voltage 5.5 5.49 5.4 5.4 v in v il or v ih 4.5 3.86 3.76 v i oh = 24 ma 5.5 4.86 4.76 i oh = 24 ma (note 6) v ol maximum low level 4.5 0.001 0.1 0.1 vi out 50 p a output voltage 5.5 0.001 0.1 0.1 v in v il or v ih 4.5 0.36 0.44 v i ol = 24 ma 5.5 0.36 0.44 i ol = 24 ma (note 6) i in maximum input 5.5 r 0.1 r 1.0 p av i v cc , gnd leakage current i cct maximum 5.5 0.6 1.5 ma v i v cc 2.1v i cc /input i old minimum dynamic 5.5 75 ma v old 1.65v max i ohd output current (note 7) 5.5 75 ma v ohd 3.85v min i cc maximum quiescent 5.5 4.0 40.0 p av in v cc supply current or gnd symbol parameter v cc t a 25 q ct a 40 q c to 85 q c units (v) c l 50 pf c l 50 pf (note 8) min typ max min max t plh propagation delay 3.3 1.5 6.0 9.5 1.0 10.5 ns 5.0 1.5 4.5 7.0 1.0 8.0 t phl propagation delay 3.3 1.5 5.5 8.5 1.0 10.0 ns 5.0 1.5 4.0 6.0 1.0 6.5 symbol parameter v cc t a 25 q ct a 40 q c to 85 q c units (v) c l 50 pf c l 50 pf (note 9) min typ max min max t plh propagation delay 5.0 1.0 6.5 9.0 1.0 10.0 ns t phl propagation delay 5.0 1.0 6.5 9.0 1.0 9.5 ns symbol parameter typ units conditions c in input capacitance 4.5 pf v cc open c pd power dissipation capacitance 25.0 pf v cc 5.0v
www.fairchildsemi.com 4 74ac10 74ACT10 physical dimensions inches (millimeters) unless otherwise noted 14-lead small outline integrated circuit (soic), jedec ms-012, 0.150" narrow package number m14a
5 www.fairchildsemi.com 74ac10 74ACT10 physical dimensions inches (millimeters) unless otherwise noted (continued) pb-free 14-lead small outline package (sop), eiaj type ii, 5.3mm wide package number m14d
www.fairchildsemi.com 6 74ac10 74ACT10 physical dimensions inches (millimeters) unless otherwise noted (continued) 14-lead thin shrink small outline package (tssop), jedec mo-153, 4.4mm wide package number mtc14
7 www.fairchildsemi.com 74ac10 74ACT10 triple 3-input nand gate physical dimensions inches (millimeters) unless otherwise noted (continued) 14-lead plastic dual-in-line package (pdip), jedec ms-001, 0.300" wide package number n14a fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fairchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild ? s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. a critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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